もっと例文: 1 2 3 4 5
- In supervisor mode, instruction addresses correspond directly to physical memory.
- Memory barrier instructions address reordering effects only at the hardware level.
- When that occurs ( the STL's next instruction address remains 0003 ) execution continues as follows:
- To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction.
- The effective address for a PC-relative instruction address is the offset parameter added to the address of the next instruction.